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ir3621 & (pbf) 1 www.irf.com data sheet no.pd60231 rev b descriptionthe ir3621 ic combines a dual synchronous buck control- ler and drivers, providing a cost-effective, high performance and flexible solution. the ir3621 operates in 2-phase mode to produce either 2-independent output voltages or current share single output for high current application. the 180 out-of-phase operation allows the reduction of input andoutput capacitance. other key features include two independently programmable soft-start functions to allow system level sequencing of out- put voltages in various configurations. the pre-bias protec- tion feature prevents the discharge of the output voltage and possible damage to the load during start-up when a pre- existing voltage is present at the output. programmable switching frequency up to 500khz per phase allows flexibil- ity to tune the operation of the ic to meet system level re- quirements, and synchronization allows the simplification of system level filter design. protection features such as selectable hiccup or latched current limit, and under voltage lock-out are provided to give required system level security in the event of a fault condition. features 2-phase / dual synchronous pwm controller with oscillator synchronization and pre-bias startup figure 1 - typical application of ir3621 in current share single output and 2-independent output voltage configuration applications embedded networking & telecom systems distributed point-of-load power architectures 2-phase power supply graphics card ddr memory applications dual synchronous controller with 180 out of phase operationconfigurable to 2-independent outputs or current share single output voltage mode control current sharing using inductor's dcr selectable hiccup or latched current limit using mosfet's r ds(on) sensing latched over-voltage protection pre-bias start up programmable switching frequency up to 500khz two independent soft-starts/shutdowns precision reference voltage 0.8v power good output external frequency synchronization thermal protection vin vout pgnd1 ldrv1 hdrv1 ldrv2 hdrv2 gnd comp2 comp1 ss1 / sd ir3621 rt ss2 / sd pgnd2 ocset2 ocset1 vin vin vout1 pgnd1 ldrv1 hdrv1 ldrv2 hdrv2 gnd comp2 comp1 ss1 / sd ir3621 rt ss2 / sd pgnd2 ocset2 ocset1 vin vout2 current share, single output configuration 2-independent output voltage configuration pkg desig mm ff part leadfree number part number ir3621m IR3621MPBF ir3621mtr ir3621mtrpbf ir3621f ir3621fpbf ir3621ftr ir3621ftrpbf parts per tube 73 ------ 50 ------ parts per reel ------ 6000 ------ 2500 ordering information pin count 3232 28 28 t & r orientation fig a downloaded from: http:///
2 ir3621 & (pbf) www.irf.com absolute maximum ratings vcc, v cl supply voltage ........................................... -0.5v to 16v vch1 and vch2 supply v oltage ................................ -0.5v to 25v pgood.................................................................... -0.5v to 16v storage temperature range ...................................... -55c to 150c junction temperature range ..................................... -40c to 150c esd classification ................................................... jedec, jesd22-a114 caution: stresses above those listed in ?absolute maximum rating? may cause permanent damage to the device. these are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifica- tions is not implied. exposure to ?absolute maximum rating? conditions for extended periods may affect device reliability package information exposed pad on underside is connected to a copperpad through vias for 4-layer pcb board design. parameter definition min max units vcc supply voltage 5.5 14.5 v vch1,2 supply voltage 10 20 v fs operating frequency 200 500 khz tj junction temperature -40 125 c ja = 75.5 c/w jc =13.3 c/w v cc comp2 rt sync vch2 hdrv2 fb2 pgnd2 hdrv1 vch1 ocset1 comp1 v sen1 ss1 / sd fb1 pgood v ref gnd 4 3 2 1 25 26 27 28 7 6 5 22 23 24 12 17 11 18 10 19 9 20 8 21 ldrv2 v cl 14 13 ldrv1 pgnd1 15 16 v p2 hiccup ocset2 ss2 / sd v sen2 v out3 ja = 36.0 c/w jc = 1.0 c/w 32-lead mlpq 5mmx5mm (m) nc 13 fb1 comp1 ss1/sd1 ocset1 vch1 pgnd2 ldrv2 v cl ldrv1 comp2 ss2/sd2 ocset2 vch2 hdrv2 v out3 vcc pgood gnd 4 5 6 7 8 9 10 11 12 17 18 19 20 21 28 29 30 31 32 pad 14 15 16 hiccup sync v sen1 22 23 24 v sen2 fb2 1 2 3 v ref v p2 nc 25 26 27 pgnd1 nc hdrv1 rt nc 28-pin tssop (f) ir3621f recommended operating conditions ir3621m & IR3621MPBF downloaded from: http:///
ir3621 & (pbf) 3 www.irf.com electrical specifications unless otherwise specified, these specifications apply over vcc=12v, vch1=vch2=v cl =12v and 0c 4 ir3621 & (pbf) www.irf.com parameter symbol test condition min typ max units v out3 internal regulator output voltage output current protection section ovp trip threshold ovp fault prop delay ocset current hiccup duty cycle hiccup high level threshold hiccup low level threshold thermal shutdown trip point thermal shutdown hysteresis output drivers section lo drive rise time hi drive rise time lo drive fall time hi drive fall time dead band time output forced to 1.25v ref note2hiccup pin pulled high, note2 note2 note2 note2 note2 c l =1500pf,figure 2 c l =1500pf, figure 2 c l =1500pf,figure 2 c l =1500pf,figure 2 see figure 2 6.25 1.15 v ref 20 5 140 2018 18 25 25 50 v ma v s a % vv c c nsns ns ns ns ovp ovp (delay) i ocset t r(lo) t r(hi) t f(lo) t f(hi) t db 5.8 44 1.1 v ref 16 2 6.7 1.2 v ref 5 24 0.8 5050 50 50 100 note 2 : guaranteed by design but not tested for production. figure 2 - rise time, fall time and deadband for driver section 9v 2v 9v 2v high side driver (hdrv) low side driver (ldrv) tr tf deadband h_to_l deadband l_to_h tr tf downloaded from: http:///
ir3621 & (pbf) 5 www.irf.com pin descriptions 12 3 4 5,236,22 7,21 8 20 9,19 10,18 11,17 12,1613,15 1424 25 26 27 28 power good pin. low when any of the outputs fall 10% below the set voltages.supply voltage for the internal blocks of the ic. the vcc slew rate should be <0.1v/us. output of the internal ldo. connect a 1.0uf capacitor from this pin to ground. connecting a resistor from this pin to ground sets the oscillator frequency. sense pins for ovp and pgood. for current share tie these pins together. inverting inputs to the error amplifiers. in current sharing mode, fb1 is con- nected to a resistor divider to set the output voltage and fb2 is connected to programming resistor to achieve current sharing. in independent 2-channel mode, these pins work as feedback inputs for each channel. compensation pins for the error amplifiers. these pins provide user programmable soft-start function for each outputs. connect external capacitors from these pins to ground to set the start up time for each output. these outputs can be shutdown independently by pulling the respective pins below 0.3v. during shutdown both mosfets will be turned off. for current share mode ss2 must be floating. a resistor from these pins to switching point will set current limit threshold. supply voltage for the high side output drivers. these are connected to voltages that must be typically 6v higher than their bus voltages. a 0.1 f high fre- quency capacitor must be connected from these pins to pgnd to provide peak drive current capability. output drivers for the high side power mosfets. note3 these pins serve as the separate grounds for mosfet drivers and should beconnected to the system?s ground plane. output drivers for the synchronous power mosfets. supply voltage for the low side output drivers. the internal oscillator can be synchronized to an external clock via this pin. when pulled high, it puts the device current limit into a hiccup mode. when pulled low, the output latches off, after an overcurrent event. non-inverting input to the second error amplifier. in the current sharing mode, it is connected to the programming resistor to achieve current sharing. in inde- pendent 2-channel mode it is connected to v ref pin when fb2 is connected to the resistor divider to set the output voltage. reference voltage. the drive capability of this pin is about 2 a. analog ground for internal reference and control circuitry. tssop mlpq pin symbol pin description 2930 31 1 2,223,21 4,20 5 19 6,187,17 8,16 10,14 11,13 1223 24 26 27 28 9,15,25.32 pgood vcc v out3 rt v sen2 , v sen1 fb2,fb1 comp2, comp1 ss2 / sdss1 / sd ocset2,ocset1 vch2, vch1 hdrv2, hdrv1 pgnd2, pgnd1 ldrv2, ldrv1 v cl sync hiccup v p2 v ref gnd n/c note3: the negative voltage at these pins may cause instability for the gate drive circuits. to prevent this, a low forward voltage drop diode (schottky) is required between these pins and power ground. no connect downloaded from: http:///
6 ir3621 & (pbf) www.irf.com figure 3 - ir3621block diagram block diagram pbias2 bias generator ldrv2 two phase oscillator 0.8v 3v ramp1 sync gnd hdrv2 vch2 ss1 / sd comp2 error amp2 pwm comp2 por v out3 28ua reset dom ldrv1 v cl hdrv1 vch1 fb1 comp1 error amp1 pwm comp1 reset dom set1 set2 ramp2 64ua max uvlo vch2 vch1 fb2 pgnd2 vcc rt 0.8v ss2 / sd v p2 v ref pgood / ovp pgood r s q q s r v sen1 v sen2 ocset2 ovp hdrv off / ldrv on thermal shutdown pgnd1 ocset1 28ua 64ua hiccup hiccup control ss1 ss2 mode regulator mode control por mode 0.8v ss 2 mode 20ua 20ua por 0.8v pbias1 0.3v ss1 q r s pbias1 ss1 ss2 3ua 3ua por 0.3v ss2 q r s por downloaded from: http:///
ir3621 & (pbf) 7 www.irf.com functional descriptionintroduction the ir3621 is a versatile device for high performance figure 4 - loss-less inductive current sensing and current sharing. in the diagram, l1 and l2 are the output inductors. r l1 and r l2 are inherent inductor resistances. the resistor r1 and capacitor c1 are used to sense the average in-ductor current. the voltage across the capacitors c1 and c2 represent the average current flowing into resis- tance r l1 and r l2 . the time constant of the rc network should be equal or at most three times larger than thetime constant l 1 /r l1 . l1 r l1 r1 l2 r l2 r2 c2 ir3621 comp 0.8v fb1 vp2 fb2 master e/a slave e/a pwm comp2 pwm comp1 c1 v out l1 r l1 r1 c1=(1~3) ---(1) figure 5 - 30a current sharing using inductor sensing (5a/div) buck converters. it consists of two synchronous buckcontrollers which can be operated either in two indepen- dent mode or in current share mode. the timing of the ic is provided by an internal oscillator circuit which generates two out-of-phase clock that can be programmed up to 500khz per phase. supply voltage vcc is the supply voltage for internal controller. the op- erating range is from 5.5v to 14.5v. it also is fed to the internal ldo. when vcc is below under-voltage thresh- old, all mosfet drivers will be turned off. internal regulator the regulator powers directly from vcc and generates a regulated voltage (typ. 6.2v@40ma). the output is pro- tected for short circuit. this voltage can be used for charge pump circuitry as shown in figure12. input supplies undervoltage lockout the ir3621 uvlo block monitors three input voltages (vcc, vch1 and vch2) to ensure reliable start up. the mosfet driver output turn off when any of the supply voltages drops below set thresholds. normal operation resumes once the supply voltages rise above the set values. mode selection the ss2 pin is used for mode selection. in current share mode this pin should be floating and in dual output mode a soft start capacitor must be connected from this pin to ground to program the start time for the second output. independent mode in this mode the ir3621 provides control to two indepen- dent output power supplies with either common or differ- ent input voltages. the output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. the error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, which are applied to the fet drivers, fig- ure19 shows a typical schematic for such application. currnt share mode this feature allows to connect both outputs together to increase current handling capability of the converter to support a common load. the current sharing can be done either using external resistors or sensing the dcr of inductors (see figure 4). in this mode, one control loop acts as a master and sets the output voltage as a regular voltage mode buck con- troller and the other control loop acts as a slave and monitors the current information for current sharing. the voltage drops across the current sense resistors (or dcr of inductors) are measured and their difference is ampli- fied by the slave error amplifier and compared with the ramp signal to generate the pwm pulses to match the output current. in this mode the ss2 pin should be float- ing. downloaded from: http:///
8 ir3621 & (pbf) www.irf.com dual soft-startthe ir3621 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. it provides a separate soft-start function for each outputs. this will enable to sequence the outputs by controlling the rise time of each output through selection of different value soft-start capacitors. the soft-start pins will be connected together for applications where, both outputs are required to ramp-up at the same time. to ensure correct start-up, the soft-start sequence ini- tiates when the vcc, vch1 and vch2 rise above their threshold and generate the power on reset (por) sig- nal. soft-start function operates by sourcing an internal current to charge an external capacitor to about 3v. ini- tially, the soft-start function clamps the e/a?s output of the pwm converter. during power up, the converter out- put starts at zero and thus the voltage at fb is about 0v. a current (64 a) injects into the fb pin and generates a voltage about 1.6v (64 a 25k) across the negative input of e/a and (see figure6).the magnitude of this current is inversely proportional to the voltage at soft-start pin. the 28 a current source starts to charge up the external capacitor. in the mean time, the soft-start voltage ramps up, the current flowing into fb pin starts to decrease linearly and so does the voltage at negative input of e/a. ss1 / sd comp2 error amp2 por 28ua fb1 comp1 error amp1 64ua max fb2 0.8v ss2 / sd 20 22 21 6 v p2 26 8 7 28ua 64ua figure 6 -soft-start circuit for ir3621 when the soft-start capacitor is around 1v, the current flowing into the fb pin is approximately 32 a. the volt- age at the positive input of the e/a is approximately:the e/a will start to operate and the output voltage starts to increase. as the soft-start capacitor voltage contin- ues to go up, the current flowing into the fb pin will keep decreasing. because the voltage at pin of e/a is regu- lated to reference voltage 0.8v, the voltage at the fb is: v fb = 0.8-(25k injected current) the feedback voltage increases linearly as the injectingcurrent goes down. the injecting current drops to zero when soft-start voltage is around 1.8v and the output voltage goes into steady state. figure 7 shows the theo- retical operational waveforms during soft-start. 32 a 25k = 0.8v soft-start voltage voltage at negative input of error amp voltage at fb pin current flowing into fb pin 64ua 0ua 0v 0.8v ? 1.6v 0.8v 0v 3v ? 1.8v ? 1v output of por figure 7 - theoretical operational waveforms during soft-start. the output start-up time is the time period when soft- start capacitor voltage increases from 1v to 1.8v. the start-up time will be dependent on the size of the exter- nal soft-start capacitor. the start-up time can be esti- mated by: 28 a t start /c ss = 1.8v-1v low temperature start-up the controller is capable of starting at -40 c ambient temperature. downloaded from: http:///
ir3621 & (pbf) 9 www.irf.com l1 r set ir3621 ocset i ocset v out hiccup control q1 q2 figure 9 - diagram of the over current sensing. v ocset = i ocset r set -r ds(on) i l ---(2) v ocset = i ocset r set - r ds(on) i l = 0 the critical inductor current can be calculated by set-ting: i set = i l(critical) = ---(3) r set i ocset r ds(on) the internal current source develops a voltage acrossr set . when the low side switch is turned on, the induc- tor current flows through the q2 and results a voltagewhich is given by: the value of r set should be checked in an actual circuit to ensure that the over current protectioncircuit activates as expected. the ir3621 current limit is designed primarily as disaster preventing, "no blow up" circuit, and is not useful as a precision current regulator. in two independent mode, the output of each channel is protected independently which means if one output is under overload or short circuit condition, the other output will remain functional. the ocp set limit can be programmed to different levels by using the external resistors. this is valid for both hiccup mode and latch up mode. in 2-phase configuration, the ocp's output depends on any one channel, which means as soon as one channel goes to overload or short circuit condition the output will enter either hiccup or latch-up, dependes on status of hiccup pin. for a given start up time, the soft-start capacitor can becalculated by: c ss ? 28 a t start /0.8v over-current protectionthe ir3621 can provide two different schemes for over- current protection (ocp). when the hiccup pin is pulled high, the ocp will operate in hiccup mode. in this mode, during overload or short circuit, the outputs enter hiccup mode and stay in that mode until the overload or short circuit is removed. the converter will automatically re- cover. when the hiccup pin is pulled low, the ocp scheme will be changed to the latch up type, in this mode the converter will be turned off during overcurrent or short circuit. the power needs to be recycled for normal operation. each phase has its own independent ocp circuitry. the ocp is performed by sensing current through the r ds(on) of low side mosfet. as shown in figure 9, an external resistor (r set ) is connected between ocset pin and the drain of low side mosfet (q2) which sets thecurrent limit set point. the soft-start is part of the over current protectionscheme, during the overload or short circuit condition the external soft start capacitors will be charged and discharged in certain slope rate to achieve the hiccup mode function. out-of-phase operationthe ir3621 drives its two output stages 180 out-of-phase. in 2-phase configuration, the two inductor ripple currentscancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same ripple voltage requirement. in single input voltage applications, the input ripple current reduces. this results in much smaller input capacitor's rms current and reduces the input capacitor quantity. ss1 / sd 20 28ua 3ua hiccup if using one soft start capacitor in dual configuration for aprecise power up the ocp needs to be set to latch mode. figure 8 - 3ua current source for discharging soft start-capacitor during hiccup mode pre-bias startupthe ir3621 allows pre-bias startup without discharging the output capacitors. the output starts in asynchro- nous fashion and keeps the synchronous mosfet off until the first gate signal for control mosfet is gener- ated. downloaded from: http:///
10 ir3621 & (pbf) www.irf.com frequency synchronizationthe ir3621 is capable of accepting an external digital synchronization signal. synchronization will be enabled by the rising edge at an external clock. per-channel switch- ing frequency is set by external resistor (rt). the free running oscillator frequency is twice the per-channel fre- quency. during synchronization, rt is selected such that the free running frequency is 20% below the sync fre- quency. synchronization capability is provided for both 2- output and 2-phase configurations. when unused, the sync pin will remain floating and is noise immune. thermal shutdown temperature sensing is provided inside ir3621. the trip threshold is typically set to 140 c. when trip threshold is exceeded, thermal shutdown turns off both mosfets. thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to normal range. there is a 20 c hysteresis in the shutdown thresh- old. shutdownthe outputs can be shutdown independently by pulling the respective soft-start pins below 0.3v. this can be easily done by using an external small signal transis- tor. during shutdown both mosfets will be turned off. during this mode the ldo will stay on. normal opera- tion will resume by cycling soft start pins. operation frequency selection power goodthe ir3621 provides a power good signal. the power good signal should be available after both outputs have reached regulation. this pin needs to be externally pulled high. high state indicates that outputs are in regulation. power good will be low if either one of the output voltages is 10% below the set value. there is only one power good for both outputs. over-voltage protection ovp over-voltage is sensed through separate v out sense pins v sen1 and v sen2 . a separate ovp circuit is provided for each output. upon over-voltage condition of either one ofthe outputs, the ovp forces a latched shutdown on both outputs. in this mode, the upper fet drivers turn off and the lower fet drivers turn on, thus crowbaring the out- puts. reset is performed by recycling vcc. error amplifier the ir3621 is a voltage mode controller. the error ampli- fiers are of transconductance type. in independent mode, each amplifier closes the loop around its own output volt- age. in current sharing mode, amplifier 1 becomes the master which regulates the common output voltage. am- plifier 2 performs the current sharing function. both am- plifiers are capable of operating with type iii compensa- tion control scheme. figure 10- switching frequency versus external resistor. the optimum operating frequency range for the ir3621is 300khz per phase, theoretically the ir3621 can be operated at higher switching frequency (e.g. 500khz). however the power dissipation for ic, which is function of applied voltage, gate drivers load and switching fre- quency, will result in higher junction temperature of de- vice. it may exceed absolute maximum rating of junc- tion temperature, figure 18 (page 17) shows case tem- perature versus switching frequency with different ca- pacitive loads for tssop package. this should be considered when using ir3621 for such application. the below equation shows the relationship between the ic's maximum power dissipation and junc- tion temperature: where: tj: maximum operating junction temperature ta: ambient temperature ja = thermal impedance of package the switching frequency is determined by an externalresistor (rt). the switching frequency is approximately inversely proportioned to resistance (see fig 10). pd = j- a ja per channel switching frequency vs. rt 0 100 200 300 400 500 600 700 0 1 02 03 04 05 06 07 0 rt ( kohm) switching frequency (khz) downloaded from: http:///
ir3621 & (pbf) 11 www.irf.com application information design example: the following example is a typical application for the ir3621, the schematic is figure19 on page18. output voltage programming output voltage is programmed by the reference voltage and an external voltage divider. the fb1 pin is the invert- ing input of the error amplifier, which is referenced to the voltage on the non-inverting pin of error amplifier. for this application, this pin (v p2 ) is connected to the reference voltage (v ref ). the output voltage is defined by using the following equation:when an external resistor divider is connected to the output as shown in figure 11. figure 11 - typical application of the ir3621 for pro- gramming the output voltage. equation (4) can be rewritten as: will result to: v out(2.5v) = 2.5v v ref = 0.8v r 9 = 2.15k, r 5 = 1k if the high value feedback resistors are used, the inputbias current of the fb pin could cause a slight increase in output voltage. the output voltage can be set more accurately by using low value, precision resistors. for a start-up time of 4ms for both output, the soft-startcapacitor will be 0.1 f. connect two 0.1 fceramic capacitors from ss1 pin and ss2 pin to gnd.supply vch1 and vch2 to drive the high side mosfet, it is necessary to sup- ply a gate voltage at least 4v greater than the bus volt- age. this is achieved by using a charge pump configu- ration as shown in figure 12. this method is simple and inexpensive. the operation of the circuit is as fol- lows: when the lower mosfet is turned on, the ca- pacitor (c1) charges up to v out3 , through the diode (d1). the bus voltage will be added to this voltage whenupper mosfet turns on in next cycle, and providing supply voltage (vch1) through diode (d2). vch1 is ap- proximately: capacitor in the range of 0.1 f is generally adequate for most applications. the diode must be a fast recov-ery device to minimize the amount of charge fed back from the charge pump capacitor into v out3 . the diodes need to be able to block the full power rail voltage, whichis seen when the high side mosfet is switched on. for low voltage application, schottky diodes can be used to minimize forward drop across the diodes at start up. figure 12 - charge pump circuit. r 6 = r 5 - 1 v out v p ( ) fb ir3621 v out r 5 r 6 v ref v p2 vch1 ? v out3 + v bus - (v d1 + v d2 ) v in = 12v v out(2.5v) = 2.5v @ 10a v out(1.8v) = 1.8v @ 10a ? v out = output voltage ripple ? 3% of v out f s = 400khz l2 ir3621 d1 c1 vch1 hdrv regulator q1 q2 v out3 c2 v bus d2 c3 css ? 28 t start ( f) ---(5) where t start is the desired start-up time (ms) v out = v p2 1 + ---(4) r 6 r 5 v p2 = v ref = 0.8v ( ) v out(1.8v) = 1.8v v ref = 0.8 r 7 = 1.24k, r 8 = 1k soft-start programmingthe soft-start timing can be programmed by selecting the soft-start capacitance value. the start-up time of the converter can be calculated by using: downloaded from: http:///
12 ir3621 & (pbf) www.irf.com for higher efficiency, low esr capacitors are recom- mended. choose two poscap from sanyo 16tpb47m (16v, 47 f, 70m ? ) with a maximum allowable ripple current of 1.4a for inputs of each channel.inductor selection the inductor is selected based on operating frequency, transient performance and allowable output voltage ripple. low inductor values result in faster response to step load (high ? i/ ? t) and smaller size but will cause larger output ripple due to increased inductor ripple current. asa rule of thumb, select an inductor that produces a ripple current of 10-40% of full load dc. for the buck converter, the inductor value for desired operating ripple current can be determined using the fol- lowing relation: v in - v out = l ; ? t = d ; d = 1 f s v out v in ? i ? t l = (v in - v out ) ---(7) v out v in ? i f s where:v in = maximum input voltage v out = output voltage ? i = inductor ripple current f s = switching frequency ? t = turn on time d = duty cycle where:? v o = output voltage ripple ? i = inductor ripple current ? v o = 3% of v o will result to esr (2.5v) =16.6m ? and esr (1.8v) =16m ? esr ---(8) ? v o ? i o the sanyo tpc series, poscap capacitor is a good choice.the 6tpc330m, 330 f, 6.3v has an esr 40m ? . se- lecting three of these capacitors in parallel for 2.5v out-put, results to an esr of ? 13.3m ? which achieves our low esr goal. and selecting three of these capacitors inparallel for 1.8v output, results in an esr of ? 13.3m ? which achieves our low esr goal.the capacitors value must be high enough to absorb the inductor's ripple current. power mosfet selection the ir3621 uses four n-channel mosfets. the selec- tion criteria to meet power transfer requirements is based on maximum drain-source voltage (v dss ), gate-source drive voltage (v gs ), maximum output current, on-resis- tance r ds(on) and thermal management. the both control and synchronous mosfets must have a maximum operating voltage (v dss ) that exceeds the maximum input voltage (v in ). input capacitor selectionthe 180 0 out of phase will reduce the rms value of the ripple current seen by input capacitors. this reducesnumbers of input capacitors. the input capacitors must be selected that can handle both the maximum ripple rms at highest ambient temperature as well as the maximum input voltage. the rms value of current ripple for duty cycles under 50% is expressed by: for ? i (2.5v) = 45%(i o(2.5v) ), then the output inductor will be: l 4 = 1.1 h for ? i (1.8v) = 35%(i o(1.8v) ), then the output inductor will be: l 3 = 1.1 h panasonic provides a range of inductors in different val-ues and low profile for large currents. output capacitor selection the criteria to select the output capacitor is normally based on the value of the effective series resistance (esr). in general, the output capacitor must have low enough esr to meet output ripple and load transient requirements, yet have high enough esr to satisfy sta- bility requirements. the esr of the output capacitor is calculated by the following relationship: i rms = (i 1 2 d 1 (1-d 1 )+i 2 2 d 2 (1-d 2 )-2i 1 i 2 d 1 d 2 ) --- (6) where:i rms is the rms value of the input capacitor current d 1 and d 2 are the duty cycle for each output i 1 and i 2 are the current for each output for this application the i rms =4.8a (esl, equivalent series inductance is neglected) choose etqp6f1r1bfa (1.1 h, 16a, 2.2m ? ) both for l 3 and l 4. for 2-phase application, equation (7) can be used forcalculating the inductors value. in such case the induc- tor ripple current is usually chosen to be between 10- 40% of maximum phase current. downloaded from: http:///
ir3621 & (pbf) 13 www.irf.com choose irf7821 for control mosfets and irf8113 for synchronous mosfets. these devices provide low on- resistance in a compact soic 8-pin package. the mosfets have the following data: the total conduction losses for each output will be: the switching loss is more difficult to calculate, even though the switching transition is well understood. the reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. the control mosfet contributes to the majority of the switch- ing losses in a synchronous buck converter. the syn- chronous mosfet turns on under zero voltage condi- tions, therefore, the switching losses for synchronous mosfet can be neglected. with a linear approxima- tion, the total switching loss can be expressed as: these values are taken under a certain condition test.for more details please refer to the irf7821 data sheet. by using equation (9), we can calculate the total switch- ing losses. programming the over-current limit the over-current threshold can be set by connecting a resistor (r set ) from drain of low side mosfet to the ocset pin. the resistor can be calculated by using equa-tion (3). the r ds(on) has a positive temperature coefficient and it should be considered for the worse case operation. p con(total, 2.5v) = p con(upper) + p con(lower) p con(total, 2.5v) = 1.0w p sw(total,2.5v) = 0.18w p sw(total,1.8v) = 0.18w irf7821v dss = 30v r ds(on) = 9m ? where:v ds(off) = drain to source voltage at off time t r = rise time t f = fall time t = switching periodi load = load current p sw = i load ---(9) v ds(off) 2 t r + t f t irf7821t r = 2.7ns t f = 7.3ns r ds(on) = 6m ? 1.5 = 9m ? i set ? i o(lim) = 10a 1.5 = 15a (50% over nominal output current)this results to: r set = r 1 =r 6 =6.75k ? v ds v gs 10% 90% t d (on) t d (off) t r t f figure 13 - switching time waveforms. from irf7821 data sheet we obtain: 22 p cond (upper switch) = i load r ds(on) d ? p cond (lower switch) = i load r ds(on) (1 - d) ? ? = r ds(on) temperature dependency the gate drive requirement is almost the same for both mosfets. logic-level transistors can be used and cau- tion should be taken with devices at very low v gs to pre- vent undesired turn-on of the complementary mosfet, which results in a shoot-through. the total power dissipation for mosfets includes con- duction and switching losses. for the buck converter, the average inductor current is equal to the dc load current. the conduction loss is defined as: the r ds(on) temperature dependency should be consid- ered for the worst case operation. this is typically givenin the mosfet data sheet. ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. p con(total, 1.8v) = p con(upper) + p con(lower) p con(total, 1.8v) = 1.0w irf81 13 v dss = 30v r ds(on) = 6m ? this resistor must be placed close to the ic, place asmall ceramic capacitor from this pin to ground for noise rejection purposes. downloaded from: http:///
14 ir3621 & (pbf) www.irf.com the esr zero of the output capacitor is expressed asfollows: figure 15 - compensation network without local feedback and its asymptotic gain plot. the transfer function (ve / v out ) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: |h(s)| is the gain at zero cross frequency. first select the desired zero-crossover frequency (f o1 ): v out vp=v ref r 5 r 9 r 4 c 9 ve e/a f z h(s) db frequency gain(db) fb comp c pole f esr = ---(10a) 1 2 esr co h(s) = g m ---(11) ( ) r 5 r 9 + r 5 1 + sr 4 c 9 sc 9 f z = ---(13) 1 2 r 4 c 9 |h(s=j 2 f o )| = g m r 4 ---(12) r 5 r 9 +r 5 feedback compensationthe ir3621 is a voltage mode controller; the control loop is a single voltage feedback path including error ampli- fier and error comparator. to achieve fast transient re- sponse and accurate output regulation, a compensation circuit is necessary. the goal of the compensation net- work is to provide a closed loop transfer function with the highest 0db crossing frequency and adequate phase margin (greater than 45 ). the output lc filter introduces a double pole, ?40db/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 (see figure 14). the reso- nant frequency of the lc filter is expressed as follows:where: lo is the output inductor for 2-phase application, the effective outputinductance should be used co is the total output capacitor figure 14 shows gain and phase of the lc filter. since we already have 180 phase shift just from the output filter, the system risks being unstable. f lc = ---(10) 1 2 l o c o gain f lc 0db phase 0 f lc -180 frequency frequency -40db/decade figure14 - gain and phase of lc filter the ir3621?s error amplifier is a differential-input transcon- ductance amplifier. the output is available for dc gain control or ac phase compensation. the e/a can be compensated with or without the use of local feedback. when operated without local feedback, the transconductance properties of the e/a become evi- dent and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp pin to ground as shown in figure 15. note that this method requires the output capacitor tohave enough esr to satisfy stability requirements. in general, the output capacitor?s esr generates a zero typically at 5khz to 50khz which is essential for an ac- ceptable phase margin. f o1 > f esr and f o1 (1/5 ~ 1/10) f s downloaded from: http:///
ir3621 & (pbf) 15 www.irf.com where:v in = maximum input voltage v osc = oscillator ramp voltage f o1 = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 5 and r 9 = resistor dividers for output voltage programmingg m = error amplifier transconductance this results to r 4 =4.8k choose r 4 =5k to cancel one of the lc filter poles, place the zero be- fore the lc filter resonant frequency pole: using equations (13) and (15) to calculate c 9 , we get: same calcuation for v 1.8v will result to: r 3 = 4.2k and c 8 = 10nf one more capacitor is sometimes added in parallel withc 9 and r 4 . this introduces one more pole which is mainly used to suppress the switching noise. the additionalpole is given by: the pole sets to one half of switching frequency which results in the capacitor c pole: c 9 ? 8.3nf; choose c 9 =8.2nf f lc = 5.06khz r 5 = 1k r 9 = 2.14k g m = 1400 mho for v 2.5v : v in = 12v v osc = 1.25v f o1 = 40khz f esr = 13.3khz r 4 = ---(14) f o1 f esr f lc 2 v osc v in r 5 + r 9 r 5 1 g m for:lo = 1.1 h co = 990 f f z ? 75%f lc f z ? 0.75 1 2 l o c o ---(15) f z = 3.61khz r 4 = 5k f p = 2 r 4 1 c 9 c pole c 9 + c pole c pole = ? for f p << f s 2 1 r 4 f s r 4 f s - 1 1 c 9 for a general solution for unconditional stability for ce-ramic output capacitor with very low esr or any type of output capacitors, in a wide range of esr values we should implement local feedback with a compensation network. the typically used compensation network for a voltage-mode controller is shown in figure 16. figure 16- compensation network with local feedback and its asymptotic gain plot. in such configuration, the transfer function is given by:the error amplifier gain is independent of the transcon- ductance under the following condition: by replacing z in and z f according to figure 16, the trans- former function can be expressed as:as known, transconductance amplifier has high imped- ance (current source) output, therefore, consider should be taken when loading the e/a output. it may exceed its source/sink output current capability, so that the ampli- fier will not be able to swing its output voltage over the necessary range. the compensation network has three poles and two ze- ros and they are expressed as follows: 1 - g m z f 1 + g m z in v e v out = g m z f >> 1 and g m z in >>1 ---(16) h(s) = 1+sr 7 (1+sr 8 c 10 ) (1+sr 7 c 11 ) [1+sc 10 (r 6 +r 8 )] [ ( )] 1 sr 6 (c 12 +c 11 ) c 12 c 11 c 12 +c 11 v out v p2 =v ref r 5 r 6 r 8 c 10 c 12 c 11 r 7 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain(db) h(s) db fb comp downloaded from: http:///
16 ir3621 & (pbf) www.irf.com cross over frequency:the stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. the consideration has been taken to satisfy condition (16) regarding transconduc- tance error amplifier. these design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. the higher the band width, the potentially faster the load tran- sient response. the dc gain will be large enough to pro- vide high dc-regulation accuracy (typically -5db to -12db). the phase margin should be greater than 45 for overall stability. based on the frequency of the zero generated by esr versus crossover frequency, the compensation type can be different. the table below shows the compensation type and location of crossover frequency. where:v in = maximum input voltage v osc = oscillator ramp voltage lo = output inductor co = total output capacitors f o = r 7 c 10 v in v osc 1 2 lo co ---(17) f p1 = 0 1 2 c 10 (r 6 + r 8 ) f z2 = ? 1 2 c 10 r 6 f z1 = 1 2 r 7 c 11 f p3 = ? 1 2 r 7 1 2 r 7 c 12 f p2 = 1 2 r 8 c 10 ( ) c 12 c 11 c 12 +c 11 details are dicussed in application note an-1043 whichcan be downloaded from the ir web-site. compensator type type ii (pi) type iii (pid) method a type iii (pid) method b location of zero crossover frequency (f o ) f lc < f esr < f o < f s /2 f lc < f o < f esr < f s /2 f lc < f o < f s /2 < f zo typical output capacitor electrolytic, tantalum tantalum, ceramicceramic table - the compensation type and location of zero crossover frequency. the slave error amplifier is a differential-input transcon- ductance amplifier, in 2-phase configuration the main goal for the slave feed back loop is to control the inductor current to match the master's inductor current as well provides highest bandwidth and adequate phase margin for overall stability. the following analysis is valid for both using external current sense resistor and using dcr of inductors. where:v in = input voltage l 2 = output inductor v osc = oscillator peak voltage g(s) = = ---(18) i l2 (s) ve(s) v in sl 2 v osc d(s) = = ve(s) r s2 i l2 (s) 1 + sc 2 r 2 sc 2 ( ) r s1 r s2 ( ) g m ---(19) l 2 l 1 c 2 r 2 r s2 r s1 ve i l2 i l1 fb2 e/a2 comp2 vp2 h(s)=[g(s) d(s) r s2 ] 1+sr 2 c 2 sc 2 ( ) ( ) g m r s1 r s2 ( ) v in sl 2 v osc h(s)=r s2 compensation for slave error amplfier for 2-phaseconfiguration the transfer function of power stage is expressed by: as shown the transfer function is a function of inductor current. the transfer function for the compensation network is given by equation (19), when using a series rc circuit as shown in figure 17: figure 17 - the pi compensation network for slave channel. the loop gain function is: downloaded from: http:///
ir3621 & (pbf) 17 www.irf.com from (20), r 2 can be express as: the power stage of current loop has a dominant pole (f p ) at frequency expressed by:f p = where r eq is the total resistance of the power stage which includes the r ds(on) of the fet switches, the dcr of inductor and shunt resistance (if it used).set the zero of compensator at 10 times the dominant pole frequency f p , the compensator capacitor, c 2 can be calculated as: h(fo) = g m r s1 r 2 =1 ---(20) v in 2 fo l 2 v osc r 2 = 2 f o2 l 2 v osc v in layout considerationthe layout is very important when designing high fre- quency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start by placing the power components. make all the connections in the top layer with wide, copper filled ar- eas. the inductor, output capacitor and the mosfet should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching. place input capacitor near to the drain of the high-side mosfet. the layout of driver section should be designed for a low resistance (a wide, short trace) and low inductance (a wide trace with ground return path directly beneath it), this directly affects the driver's performance. to reduce the esr, replace the one input capacitor with two parallel ones. the feedback part of the system should be kept away from the inductor and other noise sources and must be placed close to the ic. in multilayer pcbs, use one layer as power ground plane and have a sepa- rate control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current paths to a separate loops that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. select a zero crossover frequency for control loop (f o2 ) 1.25 times larger than zero crossover frequency for volt-age loop (f o1 ): 1 g m r s1 ---(21) f o2 ? 1.25%xf 01 figure18- case temperature (tssop package) versus switching frequency at room temperature test condition: vin=vcl=vch1=vch2=12v, capacitors used as loads for output drivers. switching frequency vs. case temp 30 40 50 60 70 80 90 200 300 400 500 600 700 fr e q ( k hz ) case temp (oc ) 100pf 1000pf 1800pf 3300pf r eq 2 l 2 r eq =r ds(on) +r l +r s f z = 10 x f p 1 2 xr 2 xf z c 2 = all design should be tested for stability to verify the cal-culated values. downloaded from: http:///
18 ir3621 & (pbf) www.irf.com figure 19 - typical application of ir3621. 12v input and two independent outputs using type 2 compensation. c10 c1 12v pgood q5 l4 q4 c5 u1 1.8v @ 10a c16 l3 r7 r4 c9 r3 c8 c3 c4 c13 c11 pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch2 vch1 vcc gnd comp2 comp1 ss1 / sd pgood v ref ir3621 q3 q2 c14 sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 r2 r1 r6 d1 c12 c15 2.5v @ 10a r9 r5 r8 c18 c17 r20 r21 v sen1 v sen1 r22 r23 v sen2 v sen2 v sen2 c20 vch2 vch2 d2 typical application downloaded from: http:///
ir3621 & (pbf) 19 www.irf.com typical application figure 20 - 2-phase operation with inductor current sensing using type 2 compensation. 12v to 1.8v @ 30a output 12v pgood q5 l4 q4 c5 u1 1.8v @ 30a r8 c16 l3 c17 r9 r7 c10 r4 c9 r3 c8 c3 c4 c13 c11 pgnd1 v cl v out3 ldrv1 hdrv1 fb1 v p2 fb2 ldrv2 hdrv2 vch1 vch2 vcc gnd comp2 comp1 ss1 / sd pgood v ref ir3621 q3 q2 c14 sync rt hiccup ss2 / sd pgnd2 ocset2 ocset1 v sen1 v sen2 r2 r1 r6 d1 c12 c18 r5 c15 r8 r7 v sen1 downloaded from: http:///
20 ir3621 & (pbf) www.irf.com typical operating characteristics vout3 vs. temperature 6.1 6.12 6.14 6.16 6.18 6.2 6.22 6.24 -50 -25 0 25 50 75 100 125 temperature (c) vout3 (v) frequency vs. temperature (rt=30.9kohm) 0 50 100 150 200 250 300 350 -50 -25 0 25 50 75 100 125 temperature (c) frequency (khz) transconductance vs. temperature 500 1000 1500 2000 2500 -50 -25 0 25 50 75 100 125 temperature (c) transconductance (umho) transconductance 1 transconductance 2 ss charge current vs. temperature 15 17 19 21 23 25 27 29 31 -50 -25 0 25 50 75 100 125 temperature (c) ss charge current (ua) ss1 ss2 vfb1 vs. temperature 0.7940 0.7960 0.7980 0.8000 0.8020 0.8040 0.8060 -50 0 50 100 150 temperature [c] vf b1 [ v] vfb2 vs. temperature 0.7940 0.7960 0.7980 0.8000 0.8020 0.8040 0.8060 -50 0 50 100 150 temperature [c] vf b2 [v] downloaded from: http:///
ir3621 & (pbf) 21 www.irf.com typical operating characteristics static supply current vs. temperature 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 temperature (c) static supply cur rent (ua) icc ich1+ich2 icl dynamic supply current vs. temperature (300khz, 1500pf) 0 5 10 15 20 25 30 -50 -25 0 25 50 75 100 125 temperature (c) dynamic supply current (ua) icc ich1+ich2 icl iocset vs. temperature 15 16 17 18 19 20 21 22 23 24 25 -50 -25 0 25 50 75 100 125 temperature (c) iocset (ua) iocset1 iocset2 deadband time vs. temperature 0 10 20 30 40 50 60 70 80 90 100 -50 -25 0 25 50 75 100 125 temperature (c) deadband time (ns) h_to_l_1 h_to_l_2 l_to_h_1 l_to_h_2 hi drive rise/fall time vs. temperature 5 10 15 20 25 30 35 -50 -25 0 25 50 75 100 125 temperature (c) rise/fall time (ns) hi dr1 rise hi dr2 ris e hi dr1 fall hi dr2 fall lo drive rise/fall time vs. temperature 5 10 15 20 25 30 35 - 5 0- 2 50 2 55 07 51 0 01 2 5 temperature (c) rise/fall time (ns) lo dr1 rise lo dr2 rise lo dr1 fall lo dr2 fall downloaded from: http:///
22 ir3621 & (pbf) www.irf.com typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, t a =room temp, no air flow unless otherwise specified. figure 21 - start up waveforms for 2.5v output ch1: vin, ch2: vout3, ch3: ss1, ch4:vo1 (2.5v) figure 22 - start up waveforms for 1.8v output ch1: vin, ch2: vout3, ch3: ss2, ch4:vo2 (1.8v) figure 23 - start up waveforms ch1: vin, ch2: vout3, ch3: vref figure 24 - vo1, vo2 and pgood ch1: vin, ch2: vo1, ch3: vo2, ch4: pgood downloaded from: http:///
ir3621 & (pbf) 23 www.irf.com typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. figure 25 - 2.5v output ch1: vin, ch2: ss1, ch3: vo1, ch4: pgood figure 26 - 1.8v output ch1: vin, ch2: ss2, ch3: vo2, ch4: pgood figure 27 - gate waveforms with 180 o out of phase ch1: hdrv1, ch2: hdrv2 figure 28 - 2.5v waveforms ch1: hdrv1, ch2: ldrv1, ch3: lx1, ch4: inductor current downloaded from: http:///
24 ir3621 & (pbf) www.irf.com figure 29 - 2.5v waveforms ch1: hdrv2, ch2: ldrv2, ch3: lx2, ch4: inductor current figure 30 - 1.8v output shorted ch1: vo1, ch2: ss2, ch3: inductor current figure 31 - 2.5v output shorted ch1: vo2, ch2: ss1, ch3: inductor current figure 32 - prebias start up ch1: ss1, ch2: vo1, ch3: ss2, ch4:vo2 typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. downloaded from: http:///
ir3621 & (pbf) 25 www.irf.com figure 33 - ss1 pin shorted to gnd ch1: ss1, ch2: hdrv1, ch3: ldrv1, ch4:vo2 figure 34 - ss2 pin shorted to gnd ch1: ss2, ch2: hdrv2, ch3: ldrv2, ch4:vo1 figure 35 - external synchronization ch1: external clock, ch2: hdrv1, ch3: hdrv2 typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. downloaded from: http:///
26 ir3621 & (pbf) www.irf.com typical operating waveforms test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. figure 36 - load transient respons for vo1 (io=0 to 10a) ch1: vo1, ch4:io1 figure 37 - load transient respons for vo1 (io=10 to 0a) ch1: vo1, ch4: io1 figure 39 - load transient respons for vo2 (io=10 to 0a) ch1: vo2, ch4: io2 figure 38 - load transient respons for vo2 (io=0 to 10a) ch1: vo2, ch4: io2 downloaded from: http:///
ir3621 & (pbf) 27 www.irf.com typical performance curves test conditions: v in =12v, v out1 =2.5v, i out1 =0-10a, v out2 =1.8v, i out2 =0-10a, fs=400khz, ta=room temp, no air flow unless otherwise specified. 12v to 2.5v and 1.8v 45 50 55 60 65 70 75 80 85 90 0 2 4 6 8 10 12 14 16 io(a) efficiency (%) 2.5v 1.8v figure 40 - efficiency for 2.5v and 1.8v outputs at room temperature and no air flow. efficiency was measured when the other output was operating at no load. downloaded from: http:///
28 ir3621 & (pbf) www.irf.com (ir3621m & IR3621MPBF) mlpq 5x5 package 32-pin symbol desig a a1a3 b d d2 e e2 el r min 0.800.00 0.18 3.30 3.30 0.30 0.09 nom 0.900.02 0.23 3.45 3.45 0.40 --- 5.00 bsc max 1.000.05 0.30 3.55 3.55 0.50 --- 5.00 bsc0.50 bsc 32-pin 5x5 note 1: details of pin #1 are optional, but must be located within the zone indicated.the identifier may be molded, or marked features. 0.20 ref note: all measurements are in millimeters. a3 a1 a e2 e d/2 d2 e l b exposed pad bottom view top view pin number 1 side view e/2 d pin 1 mark area (see note1) r downloaded from: http:///
ir3621 & (pbf) 29 www.irf.com (ir3621f) tssop package 28-pin c b a 1.0 dia e f k h j g d p o m r r1 n l q detail a detail a pin number 1 ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 this product has been designed and qualified for the industrial market. visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 1 1/29 /200 7 note: all measurements are in millimeters. min 4.300.19 9.60 --- 0.850.05 0 0.500.09 0.09 nom 4.40 --- 9.70 --- 0.90 ------ 0.60 ------ 0.20 max 4.500.30 9.80 1.10 0.95 0.15 8 0.75 ------ 0.65 bsc6.40 bsc 1.001.00 12 ref 12 ref 1.00 ref 28-pin symbol desig a b cd e f gh j k l mn o p qr r1 figure a : feed direction 1 1 1 tape & reel orientation downloaded from: http:///

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